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Old 29th May 2020, 6:22 pm   #1
dominicbeesley
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Join Date: Nov 2004
Location: Hebden Bridge, West Yorkshire, UK.
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Default SC/MP timing and microcode information

Hello scampers, I've been inspired by some of the SC/MP threads over the past year or so on here and I decided to have a go at implementing an SC/MP in Verilog (I'm just learning Verilog).

I have a number of questions but first up is the bus timings - there is some quite sparse documentation on the relationship between the clock output and the ADS signal in the datasheets but must of the timing diagrams ignore the clock - does anyone have a good source of timing diagrams showing the clock (either for SC/MP I or II).

The next one is the microcode program - I've had a really quick guess at how that might work and I've got a naive version going to just do op-code fetches but I would really like to know how it was done in the original if anyone knows.

For instance I've got a separate microcode line for each clock cycle so it is something like

1 ) increment addr/p0
2 ) assert ADS/D=A12:8,Flags=R,I
3 ) assert RD, latch D to opcode reg
4 ) check top bit of opcode and branch if 0
5 ) increment addr/p0
6 ) etc

I'm not sure how the microcode would have been done on the original i.e. would there be a microcode "line" for each of these or would they be grouped together into general i.e.

1) opcode read
2) 2nd instruction byte read?

Learning a lot, but making up more as I go along! I've no idea if anything like this would have been published but may well have ended up on a university syallabus or something at some point?

D
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