[tubesrule]

Mixing types is really up to the VHDL implementation, but never a good thing to do. Comparing a SLV to an Integer may work as expected, may not work as expected or may generate a fault. There are two ways to handle this, the first being what Jeff showed:

hcs >= "0000111111"

Alternatively you can recast the SLV

conv_integer_range(hcs) >= 63

Both of these methods explicitly tell VHDL what your intent is.

Now with that said, the Xilinx tools would actually work with your original implementation mixing the SLV and Integer, but just because it works now, does not guarantee it will work in a future release. I can think of a few issues, like requiring a When Others in a Case statement in the latest releases when it wasn't required years ago, so it's always best to be explicit.

Darryl