Re: 819 line standards convertor.
Some comments on your VHDL.
There is no need for async reset "raz".
Always use synchronous design where possible. For example:
You wrote:
hsync <= '0' when (hcs < 63) else '1';
A better idea is to put this within a clocked process:
if hcs < 63 then hsync <= '0';
else hsync <= '1';
endif;
You have a clock prescaler (Diviseur de frequence d'horloge). I do not understand why. Is MCLK 50MHz? All Spartan 3 Xilinxes will clock everything at 50MHz with no timing problems.
I have attached part of a recent VHDL design. It is for a multistandard colour black generator. Much of this design is complicated and not relevant to your requirements. The useful part for you is a 625/525 pulse generator. For example lines 402 to 414 generate the mixed sync waveform. The clock is 54MHz for standard definition.
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