Quote:
Originally Posted by ScottishColin
OK - so if each 'large' horizontal line is 50ms, then I reckon about 1.35 x 50ms = 67.5ms between falling edges.
And the active CS pulse is about 0.1 * 50ms = 5ms.
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Have another look. There are over two divisions between each falling edge, each division = 50mS so that's at least 100mS and more between falling edges. Try again.
The smaller ticks divide the large divisions into fifths, so one subdivision is one fifth of 50mS (=10mS). So how long is the active-low _CE pulse?
As to active low / active high, in the retro computer world chip select signals are usually (but not always) active low, that is they hang around up at logic 1 when inactive and only perform their designated function when taken low, to 0V.
There is a handy way to tell, when looking at circuit diagrams, whether an IC pin or a signal line is active low. If it is active low the pin or line name will have an 'overline' (as opposed to an underline) over the name. The attached close up of UD9 shows two signal or pin names which are active low, and one which is not.
In plain text like this, active-low signals are often indicated by putting an underscore in front of the signal name like this '_CS', or a forward slash, like this, '/CS'.