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cmjones01 · 3rd Nov 2011, 5:01 pm

Are vsync and mclk synchronized in this design? For example, is mclk generated by a PLL locked to the incoming video? If not, then your code leads to a race condition where the length of the vsync_reset pulse depends on the exact timing between the edges of vsync and mclk, which could be anything between a whole cycle of mclk and 0. This could mean that vsync_reset is unreliable.

If they are synchronised, and any jitter on vsync is small compared with the period of mclk, then you should have no problem.

3rd Nov 2011, 5:01 pm	#100
cmjones01 Nonode Join Date: Oct 2008 Location: Warsaw, Poland and Cambridge, UK Posts: 2,677	Re: 819 line standards convertor. Are vsync and mclk synchronized in this design? For example, is mclk generated by a PLL locked to the incoming video? If not, then your code leads to a race condition where the length of the vsync_reset pulse depends on the exact timing between the edges of vsync and mclk, which could be anything between a whole cycle of mclk and 0. This could mean that vsync_reset is unreliable. If they are synchronised, and any jitter on vsync is small compared with the period of mclk, then you should have no problem.