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pitbuell94 · 2nd Nov 2011, 5:51 pm

Hi Dear all,

I meet actually a big problem with one of my internal signal.

I need to create a reset signal for the complet design.

This signal (raz_int) is an addition of an hardware reset (raz)=> easy => resistor and condensator and a signal coming from the LM1881 (vsync)=> the vsync signal from LM1881.

raz_int <= raz or vsync_rst;

The problem is that the signal coming from the LM1881 is hight for 230µs so, medesign run in a wrong way

What I want is when the vsync signal come up, a pulse around 40 or 80 nS comes.

The mclk period is 20nS.
vsync_rst is the signal I want=>pulse around 1 or 2 mclk period derivated from the rising edge of vsync.

I create this code below but XILINX give me the following information.

process(mclk, raz)--
begin
if raz = '1' then --hardware reset
vsync_rst <= '0';
elsif (vsync'event and vsync = '1' and mclk ='1')then
vsync_rst <= '1';
else vsync_rst <= '0';
end if;
end process;

ERROR:Xst:827: - "D:/Documents and Settings/Convertisseur_819_lignes/driver_625_avant_implemenatation.vhd" line 94: Signal vsync_rst cannot be synthesized, bad synchronous description. The description style you are using to describe a synchronous element (register, memory, etc.) is not supported in the current software release.

Thank you for our support.

Fred.

2nd Nov 2011, 5:51 pm	#95
pitbuell94 Retired Dormant Member Join Date: May 2009 Location: Fresnes, France Posts: 124	Re: 819 line standards convertor. Hi Dear all, I meet actually a big problem with one of my internal signal. I need to create a reset signal for the complet design. This signal (raz_int) is an addition of an hardware reset (raz)=> easy => resistor and condensator and a signal coming from the LM1881 (vsync)=> the vsync signal from LM1881. raz_int <= raz or vsync_rst; The problem is that the signal coming from the LM1881 is hight for 230µs so, medesign run in a wrong way What I want is when the vsync signal come up, a pulse around 40 or 80 nS comes. The mclk period is 20nS. vsync_rst is the signal I want=>pulse around 1 or 2 mclk period derivated from the rising edge of vsync. I create this code below but XILINX give me the following information. process(mclk, raz)-- begin if raz = '1' then --hardware reset vsync_rst <= '0'; elsif (vsync'event and vsync = '1' and mclk ='1')then vsync_rst <= '1'; else vsync_rst <= '0'; end if; end process; ERROR:Xst:827: - "D:/Documents and Settings/Convertisseur_819_lignes/driver_625_avant_implemenatation.vhd" line 94: Signal vsync_rst cannot be synthesized, bad synchronous description. The description style you are using to describe a synchronous element (register, memory, etc.) is not supported in the current software release. Thank you for our support. Fred.