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Old 29th Jun 2019, 5:19 pm   #127
NealCrook
Tetrode
 
Join Date: May 2019
Location: Reading, Berkshire, UK.
Posts: 51
Default Re: Gemini 80-Bus System

John,

here is a simple program loop. If you have a 2-channel scope you should be able to trigger on /IOREQ. It should loop after <100 clock cycles.

If it's looping OK, you can use the other channel to probe around to see chip selects on each of the memories, on the 6845, on the buffers used for the kbd and status ports and on the latch used for the write status port. You should also be able to see the low 6 bits of the address bus toggling, and see the data toggling and propagating though the buffers.

I'm assuming you can figure out the details of what to look at on the schematic, but if you need more details, let me know.

Code:
# File ivc_test1.asm
0000                    ;;; ivc_test1.asm 
0000                    ;;; simple loop for hw debug of once-working now faulty IVC 
0000                    ;;; 
0000                     
0000                            ;; in ROM and executes from reset. 
0000                            ;; assume no stack/working RAM so no subroutines 
0000                            ORG 0 
0000                     
0000 db 00              loop:   in a, (0)               ; should generate /CS to 6845. Also, use as 'scope trigger 
0002 21 00 20                   ld hl, 0x2000           ; video RAM 
0005 7e                         ld a, (hl)              ; read then write 
0006 77                         ld (hl), a 
0007 21 00 40                   ld hl, 0x4000           ; char gen ROM or RAM 
000a 7e                         ld a, (hl)              ; read then write 
000b 77                         ld (hl), a 
000c 21 00 60                   ld hl, 0x6000           ; status read 
000f 7e                         ld a, (hl)              ; read 
0010 21 00 80                   ld hl, 0x8000           ; keyboard 
0013 7e                         ld a, (hl)              ; read 
0014 21 00 a0                   ld hl, 0xa000           ; host comms data port 
0017 7e                         ld a, (hl)              ; read then write 
0018 77                         ld (hl), a 
0019 21 00 c0                   ld hl, 0xc000           ; status write 
001c af                         xor a 
001d 77                         ld (hl), a              ; write 0 
001e 21 00 e0                   ld hl, 0xe000           ; workspace RAM 
0021 7e                         ld a, (hl)              ; read then write 
0022 77                         ld (hl), a 
0023 18 db                      jr loop 
0025                     
# End of file ivc_test1.asm
The processor sub-system is very straightforward so if this code doesn't even loop there's a fundamental problem with the CPU/clock/reset/address/data signals. If that's the case the next experiment is to take the R24/D1 junction to GND (hold the chip in reset) then
probe to see:

/MREQ /RD both asserted
Address bus 0
ROM chip-selected
data bus reads 0xDB (if this ROM is fitted) or 0x31 if the standard ROM is fitted.

You should also check that you've got CLK on the Z80 and both CLK and E on the 6845.

regards,

Neal
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