Thread: Franklin VFO ?
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Old 22nd May 2019, 10:52 pm   #59
G0HZU_JMR
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Join Date: Sep 2010
Location: Cheltenham, Gloucestershire, UK.
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Default Re: Franklin VFO ?

Here's a plot of the MMIC phase noise at a much lower power level and the corresponding Leeson simulation graph. In this case the feedback attenuation is 5dB so the power arriving at the resonator is -8.8 -5 = -13.8dBm. The MMIC was biased at a lower current (down to 24mA from 40mA) and this appears to have removed nearly all the flicker noise on the E5052A plot. So I turned down the flicker corner frequency in the simulation to make the two curves match better. I don't think this is cheating but I was surprised to see the 30dB/decade flicker slope vanish from the E5052A measurement of the real MMIC oscillator.

The overall phase noise is just over 20dB higher. The resonator power is 22.8dB lower and the flicker contribution is less so it looks like the noise is about 20dB or so worse in most places just as predicted by the Leeson graph on the right. The MMIC isn't oscillating reliably in this case but it does show that the noise still follows theory even when the MMIC is oscillating at a very low level that is way off its normal compression point.

This stuff is all a bit nerdy but the aim here is to show that the phase noise of an oscillator can still be quite reasonable even at a low level of energy storage in the resonator. This last example is at a resonator input power of -14dBm and the phase noise is still reasonable for ham use as it is probably better than a lot of 1980s and 1990's (synthesised) HF transceivers.

I did try adjusting the the Franklin oscillator circuit up to 10.7MHz today and I also reduced the size of the coupling caps and took some plots with the E5052A. Sadly I goofed up on the plot transfer to FDD. I'm hoping they are
still on the internal HDD. But the results weren't that great. I used a 100pF resonator cap and there was about 15Vpkpk in the resonator at 10.7MHz. So I think there was about +5dBm in the resonator. Sadly, the phase noise was a bit disappointing. From memory, it only managed about -113dBc/Hz at 1kHz and about -135dBc/Hz at 10kHz offsets. Also, the phase noise was a bit floaty and inconsistent in this region. So something wasn't right. I couldn't see any obvious instability but the second JFET showed some clamping of the waveform at the gate. I think there may have been too much loop gain. I think this is the junction going into forward conduction and maybe this affects the phase noise a bit. It seemed about 10dB worse than predicted by Leeson. Also, I'm not sure how much the stray RC time constants in the loop affect the response at these higher frequencies. This oscillator definitely needed a bit of optimising but I really don't want to spend much time on it. I'm not sure the basic circuit is ideal and I think it needs to be designed to make the loop gain more predictable and also to minimise any clamping in the second JFET.
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Regards, Jeremy G0HZU

Last edited by G0HZU_JMR; 22nd May 2019 at 10:58 pm.
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