Quote:
Originally Posted by Duke_Nukem
If nothing else fill a ROM with NOP instructions (0x90 hex), you should then at least see consistant signals on the address line as the processor walks through the ROM.
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Not too sure about that value, DN - I thought NOP in 8085 and Z80 was 0x00?
I would, also, make the third last byte in the eprom 0xC3 so that the last three bytes at the top end are C3 00 00, meaning, 'Jump back to address 0000'.
If you don't do that the processor will run through the NOPs in the EPROM just once and then hurtle off out of control as it starts executing whatever jumps and conditional jumps it finds in the random content of the RAM.
However, using the NOP + Jump to zero trick in an EPROM will limit the range of addresses being scanned through to whatever area is occupied by the EPROM and still won't be a good test for the upper address lines.
To do that you'd need to add something which forces '00' (NOP) to be read by the CPU no matter what address is being accessed. You could do that by wiring a buffer (74LS244? 74LS245?) with all its outputs to the data lines, all its inputs held low and its enable pin enabled by combining _RD and _MREQ. Every other memory mapped device (such as Memory / Peripheral ICs) with their data pins sitting on D0-D7 would have to be removed for this test otherwise they would clash with the 'NOP' buffer as the address ran through their activation address range.
For a cruder version of the above, just take a DIL socket of the appropriate size and fit lowish value resistors (100R, say) from each data line to ground and plug it into the EPROM socket. As above, you'd have to remove every other memory mapped device from the data bus to stop them from activating and (potentially) placing unwanted data on the bus.