Quote:
Originally Posted by retroteck
The design was quite clever in certain respects. In the days before fast FIFO memory was widely available the circuit used 16 x 200nS access time static ram chips, two for each of the 8 bit ADC data lines. Because of the slow access time of these rams it meant storing 8 consecutive samples of each of the 8 ADC bits serially into latches and then writing the parallel output of these into memory every 500 nS or so.
Similarly for reading, each ram chip outputed data to an 8 to 1 data selector and was clocked out serially to the approprate DAC input data line.
Using static ram obviously meant generating seperate read and write addresses for the memory as well.
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The technique you're describing was used in the Quantel DFS1751 frame synchroniser. It was the leading steady workhorse throughout the broadcast industry in the early/mid 80's. Memory chips in the day didn't have enough speed to be 'loaded' serially and so Quantel adopted a parallel load method - I think it was called 'barrell loading'? - sequentially pop the serial samples into a line of latches then 'barrell' load them all in the memory chips at the same time.