[G0HZU_JMR]

Alan kindly sent me the schematic for the Practical Wireless version he is working on and I've attached it below in a word doc. Hopefully it will appear less fuzzy on the forum thread when uploaded in a word doc format compared to a jpg or gif.

I spotted a couple of connections that were missing and I've added these in red and also a couple of earth symbols were missing but these are just cosmetic. I've added a few bits of info on there and Alan advised me that R24 is 10nF and R41 is 40Meg (4 x 10Meg).

It looks like it mixes in a 200kHz signal at the MC1496 chip and this will generate a 2kHz heterodyne that goes through the op amp amplifier/limiter. It looks like the opamp section is a tuned 2kHz BPF with the CF set by R19.

The S meter circuit looks a bit odd because R21 looks to be a very large value and it's tapped into the early part of the 2kHz IF strip. I would have expected it to be connected further down where the signal is bigger?

The 74HC390 divider circuits look OK for the 200kHz and 2kHz taps and the MC1496 connections look 'reasonable' but I don't have any experience in using it in a circuit like this. I suppose you could test the lock performance by disconnecting the receiver section and forcing an accurate 2kHz into the opamp stage and then watch and wait to see if it eventually starts to lock in. The lock process is probably going to be quite slow even with the speed up diodes D6 and D7? But you will need to have a very accurate 2.00000kHz test source, ideally synthesised from a stable reference accurate to a few ppm. Otherwise this basic test will fail as the lock frequency will fall outside the very narrow tuning range of the 10MHz VCXO circuit.