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So, will you now work these changes into your replica?
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To be honest I'd worked out how they might have done it whilst not getting to sleep (insomnia isnt all bad!) before I read your document, but it confirmed my thoughts.
I'd like to roll these changes in, as I might as well build a rev 5, but I might need one of the AND gates for the RAM enable line, actual MM2111 ram chips are proving hard to find and the pin-compatible(ish) IM65X62 that I have managed to acquire from Poland requires the enable pin to be pulled low in read and write cycles. Unless I can liberate another of the inverters from the reset logic and invert the 'rds or wds' line, but I'm not sure the SCMP will like a slow rising reset pulse!
I might have to breadboard up a test circuit to check it can be made to work timing wise!