Hi PPPPenguin and Daryl,
I meet actually a problem concerning simulation of my FIFO.
I'm able to run correctly ISIM in XILINX ISE with all my design but not at all concerning simulation of my FIFO.
In attached document, this is the design of my workbench.
It's not complet=> just clock signal at this moment because nothing run.
I put the same frequency for both clock => RD_clk and WR_clk.
No signal move on the screen.
Do I forget very stupid stimuli
Thank you very much for your help.
Frédéric.