Hi Darryl and PPPPenguin,
Make this converter seems to be a nightmare
.
In fact, the hard part with TDA8708, LM1881 and TDA8702 is not a big issue.
All the part are on a board but nothing run
. (nothing burn too
).
The main and the big issue is the software to drive all the function.
Well, I need some information.
When I design my VHDL code, I suppose I build the design of the read part and write part as 2 single separate design part?
Only a signal coming from the write part give the information to the read part that there is some data ready to read.
In my design, after 2 lines comes, I want to start the read part.
Of course, I need to calculate the time needed to have good synchro signal between 819 and 625.
Let me explain my point of view :
Because I start to read 819 signal after 2 lines coming from 625 and because the video signal comes at line 23, I start to read line for 819 signal at the start of line 25.( I need a minimun of 2 lines to start my process...).
So, this time need 64µs * 25 line => 1536 µs.
The VBI for 819 is equal to 38 lines * 48,84 => 1855,92µs.
Then, 1855,92 - 1536 => 319,92 µs.
319, 92 µs / 64 µs => 4, 998 lines
So, the start of field one in 819 starts at the beginning of line 621 of 625 lines standart.
Is-this correct or do I drink too much
?
If I start my read process at line 621, in fact, I loose the first picture coming in the system, but normaly the rest of the process should be well synchronised, isn't it?
Have a good night.
Frederic Cabanes.