[tubesrule]

Designing Full and Empty logic within two clock domains is not trivial, especially if no other parameters are know. If for instance one the the clocks or clock enables is known to be much slower than the other, a "valid" signal can be generated to tell the higher speed clock when it's safe to read the slower address counter since you know it won't be changing. Another method is to take multiple readings of the slower address counter with the higher speed clock and compare them to make sure you have a stable reading. This latter approach only works if the higher speed clock is much faster then the lower speed clock (>3X).

As Jeff points out, it is much better to eliminate the need for Full and Empty signals by design. Sometimes this is not possible, but many times data entering and leaving the memory are in known blocks, so this can be used to your advantage. Since you know you will only be moving data into the memory at a fixed rate during an input field, and only be moving data out of the memory at a fixed rate during an output field, this can be used to your advantage. If you guarantee by design that the start of the output field is later than the input field, and there is enough memory so the read and write pointers can never collide, than you have no need for Full and Empty flags.

Keep in mind that this metastability issue is not unique to fpga's but affects all logic design with multiple clocks, and with 16 global clocks available in a typical fpga, it's just easier for this to happen.

Darryl