[SiriusHardware]

I think the BANK SEL signal should be active-high whenever an address in the system RAM address range is being read from or written to, this signal being decoded from the high address lines by one section of UB2, 7425 (input pins 9,10,12,13, output pin 8).

This BANK SEL output is in turn taken to one of the inputs of UG7, 74LS10, (inputs: 9,10,11, output: 8) which combines the BANK SEL signal with the buffered read / write signal 'B R/W' so that read pulses for the system RAM only occur during a read from the system RAM address block.

We aren't getting the read enable pulses for the system RAM out of UG7.

I note also that the BANK SEL signal feeds back to the main timing chain on sheet 6, and interestingly, it is also one of the initial inputs to the RAS/ CAS generation circuit.

BANK SEL and BØ2 (Buffered Φ2) go into UH5, 74LS00, (pins 2,1), output from UH5 pin 3 goes into pin 15 of UH4 which is at the heart of the RAS / CAS generator circuit - so a lack of BANK SEL signal could disable all of this as well as the system RAM read signal.

So the first question arising from all of that is: Is there any activity at all on the BANK SEL signal line, UB2 pin 8? - this is with the NOP test still running.

Edit: And Colin has just answered that question (pin 11 of UG7 is the same point as UB2 pin 8) - so we don't have a BANK SEL signal. This is a promising lead.

You know the jumpers on the mainboard, do they look as they have ever been tampered with or altered from their original settings? My understanding is that they are metal links which were either cut or left linked as required.