[retroteck]

Hi Argus25

Reading your posting has inspired me for ideas on further design work for a stand alone
timebase corrector.

Some 30 years ago i embarked on a framestore project from an article published by an
electronics club in the uk.

The design was quite clever in certain respects. In the days before fast FIFO memory was
widely available the circuit used 16 x 200nS access time static ram chips, two for each of the
8 bit ADC data lines. Because of the slow access time of these rams it meant storing
8 consecutive samples of each of the 8 ADC bits serially into latches and then writing the
parallel output of these into memory every 500 nS or so.
Similarly for reading, each ram chip outputed data to an 8 to 1 data selector and was clocked
out serially to the approprate DAC input data line.
Using static ram obviously meant generating seperate read and write addresses for the
memory as well.

While the basic block design was sound enough I could never get this circuit to work properly,
(clock generator and numerous timing problems), due to some of the circuit techniques
employed in some of the stages, so i eventually abanded it.

However i recently resurected the project but quickly realised that i would like to design a new
circuit from scratch. Your posting has renewed my enthusiasm for this project and i am
thinking on the lines of developing a stand alone framestore\timebase corrector.
Also i always wanted something that was not tied to a pc.

Rod