I have taken the binary and found the divide ratios for each step.
They make perfect sense provided that the main loop (10kHz one) is programmed to step between 145.528 and 145.529.
Doing that seems a little odd but who is to say what offsets are being taken out here - the designer had a free hand.
I'm pleased the table started with a division of 815 - see back at Post #7!!
To confirm it might be interesting to see what happens over the next 10kHz by repeating the exercise between 145.530 and 145.539 kHz. At least an abbreviated test to see if pins 7,8,9,&10 follow the same pattern would be interesting.
I think all this points to the uP and the 4094 shift registers being blameless. The trouble is almost certainly inside the works of TC9122, Q3005. It is not dividing by what it is being told.
It might be an idea to look into their availability.
