[Sean Williams]

I have this information from the German Lo3000 Manual - the Cheetah is a clone of this, both produced by ITT-Creed.

The screen receives its image signals via a ribbon cable from the printed circuit board monitor control (VDCB).
The task of the VDCB is to convert the data of the CPU (*) into control signals.
The data of the CPU reach the 2K RAM of the VDCB via the RAM access control. On
Address multiplexer switches either internal, or the addresses of the CPU to the RAM memory. The memory
is divided into 16 blocks of 128 bytes. The first block (0) contains the character data, such as number of characters per
Line, Scroll (**) information, number of the selected RAM block. Blocks 1-15 each contain the
Character data of a line. The character data is composed of character and feature code. Of the
Feature code contains information about the way a character is represented, e.g. underlined, inverse, bright
etc. 14 lines are displayed on the monitor. The lines are divided into 16 Raster grid lines®. The horizontal
Division of a character is either 9 or 10 pixels per character (80 or 72 characters per line;
5.17).
Fig. 5/17 .: Character representation

When a line is displayed, the line start information (line length, RAM block selection, etc.) is first entered in
Screen RAM address generator stored.
The character clock generator clocks a counter that generates the RAM addresses. About the address multiplexer and the
Feature address generation, an address is selected in the RAM memory. The row and row address generator
generates part of the address for the character PROM (grid line addresses). The characters and feature codes
The RAM is cached and synchronized. In addition, the feature code is still
decodes, since a feature code contains the information for two characters. The character code forms the remaining one
Part of the character PROM address. The data of the EPROM is converted into serial information. Last
The serial character information is synchronized with feature generation. At the exit of the VDCB
then arises the image signal VIDEO +.
Furthermore, the synchronization signals are generated in the screen control. Horizontal synchronization
(LSYNC -) and vertical synchronization (FRSY +). Other control signals are READY (VDCB Ready), CSVDC
(Selection of CPU), IRVDC (interrupt to CPU) and TIVDC (flashing).
The character generator is normally populated with a 2K byte EPROM (e.g., 2716). As an option, a 2.
Character set possible. A 4K EPROM (e.g., 2732) must then be used. The 7th bit of the character code
then selects the character set. Normally (2 Kbytes), the 7th bit contains the flashing status when using a LO 3000
4 kbyte memory no flashing of characters possible.
The screen consists of three functional units:
From the cathode ray tube, the deflection system and the display driver VDD (Visual Display Drive
Board). The VDD generates the necessary voltages for the beam generation of the picture tube. In addition, the
Synchronization signals of the VDCB used for horizontal and vertical beam deflection (by coils). The
Video signal controls the cathode of the tube via amplifier (light-dark keying). The 11 kV anode voltage will
generated by a transformer. The brightness can be pre-set on the VDD and by an external potentiometer of the
Be reset. The power supply provides a direct power supply (12V DC)
Display driver board.
*) (central control electronics)
**) Scroll: Image shift.
Hardscroll = gradual shift
Softscroll = even shift

Of course I think some context is missing due to machine translation.

Sadly no schematics exist it seems