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Old 26th Jan 2019, 12:28 am   #1
Semir_DE's Avatar
Join Date: Jan 2019
Location: Heusenstamm, (Near Frankfurt am Main), Germany.
Posts: 35
Default Sync Signal Generator for 441 Line TV System

Dear All,

This sync pulse generator is the first project I would like to introduce in this forum in the hope some of you might find it useful. It is part of a larger standards converter project I am working on at the moment. Another application I have in mind for this generator is to build a test signal generator for 441 and 405 line standards with cross hatch, grey scale, circle and other images.

This sync pulse generator supplies a variety of pulses for the old 441 line TV standard used in Germany in the late 1930's. Vintage TVs like the E1 "Einheitsfernseher" were built to support this standard. Here is a brief overview of the specifications of the 441 line TV standard that I have found on line. Should any of these parameters be incorrect I would appreciate your feedback:

- FH = 11.025 kHz, Line duration = 90.7µs
- Line Sync duration = 9µs, Front Porch = 1µs, back porch = 6.4µs
- Line Blanking = 16.4µs
- Active line duration = 74.3µs

- FV = 50Hz, 2:1 interlace
- Field Sync = 8 broad pulses 36.3µs wide
- Field Blanking 29 lines
- Active lines = 383

Since the whole design is based upon programmable logic ICs it can easily be modified to generate 405 signals as well. The circuit has the following properties:

- Can be used with master clocks of 256xFH (FH = Horizontal Frequency), 512xFH or 1024xFH
- Horizontal frequency outputs: H-Sync, H-Blanking, H-Drive, back porch Clamp
- Vertical frequency outputs: V-Sync, V-Blanking, V-Drive
- Other outputs: Composite Sync, Composite Blanking, 256xFH Clock
- Inputs: H-Reset, V-Reset, Master Clock, Alternative Clock
- Control Inputs: Clock Select CS#1/2, Equalizing Pulse enable, Blanking duration

Circuit design and tools required:

The circuit consists of two Atmel ATF750CL PLDs (Programmable Logic Device). One contains an 8 bit counter and the decoding logic for the line pulses the other has all the logic and counters for the vertical pulses programmed into it. While these are quite old ICs they can still be obtained from suppliers like Mouser or on Aliexpress for around 2-3€ each. The program code was written in CUPL on the freely available software “WinCUPL”. For programming the chips I used a GALEP4 programmer. Unfortunately the cheaper TL866 programmers do not support these chips. I have also designed a version of this project using 3 regular GAL programmable chips two GAL16v8 and one GAL20v8 and one 4040 CMOS counter. This version also seems to work very well and costs only a few pennies. Depending on how much interest this thread generates I might post that project as well…

Please contact me for the source code and/or JEDEC files for the chips.

Line pulse generation:

Let’s take a look at the way the horizontal pulses are being derived from the various counter outputs of the 8 bit horizontal counter. The attached image “Fig. 1” shows an overview of the whole generator. In Fig.2 the horizontal part is shown. The horizontal processor chip has a 2 bit prescaler counter which can divide the incoming master clock by 1, 2 or 4 depending on the setting of the “Clock Select” Jumpers CS1/CS2. This allows the circuit to be operated with master clocks of 256xFH, 512xFH or 1024xFH.

By a stroke of luck the line frequency of 11.025kHz is exactly Ľ of the sampling rate of the CD audio system. Due to this fact there are some crystals readily available on the market with frequencies of 256, 512, 768, 1024 and 2048 times the line frequency. In this design a crystal with a frequency of 2822.4kHz was used as the master clock.

A synchronous 8 bit counter in the horizontal processor divides the master clock by 2,4,...256 yielding 8 trains of square pulses with multiples of the clock duration of approx. 0.355µs. In Fig. 3 these are designated A0-A7.

The decoding logic in the horizontal processor decodes the desired pulses from the 8 counter outputs A0-A7. The line sync for example consists of 25 elements of the clock duration i.e. 25x0.355µs which gives a total duration of 8.875µs – close enough to the required 9µs for the line sync. To illustrate the process in Fig.3 I have given each chunk of the sync a different colour both in the counter output section and on the sync pulse itself. Each coloured chunk represents a decoding term in the software program of the horizontal processor:

H-SYNC = (A0 & !A1 & !A2 & A3 & A4 & !A5 & !A6 & !A7) purple chunk
+ (A1 & !A2 & A3 & A4 & !A5 & !A6 & !A7) grey chunk
+ (A2 & A3 & A4 & !A5 & !A6 & !A7) brown chunk
+ (!A4 & A5 & !A6 & !A7) turquoise chunk
+ (!A1 & !A2 & !A3 & A4 & A5 & !A6 & !A7) yellow chunk

Rem.: !Ax = Inverted Ax

This system allows for great variations in timing schemes and can be tweaked at any time by simply adjusting the decoding terms in the PLDs program code. A version for 405 lines could easily be made by using a readily available 10,368kHz crystal as the master clock. This is 1024 xFH, so the prescaler would have to be set to divide by a factor of 4 in this case. I am planning to write the code in CUPL for 405 as well and will post it here when it is ready.

Field pulse generation:

The second ATF750CL houses the complete vertical processing logic. This consists of a 9 bit divide by 441 counter, field decoding logic and additional logic to generate composite sync and blanking. The concept is shown in Fig. 4.

In order to get a precisely interlaced image the vertical pulses are being derived from a clock running at twice the horizontal rate i.e. 22.05 kHz. Unlike the counter in the horizontal section the counter used here can not be allowed to run up to the final counting state of 511 but rather has to be reset when it reaches a count of 441. A dedicated decoding string in the program of this processor detects the 441st counting state and resets the counter back to “0” hence the counter can only run through values of 0...440 which is exactly 441 states corresponding to the 441 lines of the signal. Decoding of the vertical pulses is done in exactly the same manner as with the line pulses. Fig. 5 shows the process e.g. the blanking signal in this format is 29 lines and consists of the yellow, light brown and dark brown as well as purple chunks put together.

Historically this TV system never had equalizing pulses. For the sake of experimenting and testing I decided to add some anyway. The helper signal “EQ gate” allows for 4 equalizing pulses to be inserted before and after the field sync. This setting can be changed by a jumper connected to a pin on the vertical processor chip. I currently use a modified CCTV monitor to view the signals from my generator. Activating the equalizing pulses does not seem to have a great effect on the displayed raster, but I will check once I have real images to display.

The circuit diagram can be found in the attachment.


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Attached Files
File Type: zip 441-Sync Generator - (347.1 KB, 63 views)
File Type: pdf 441_PLD-SSG.pdf (46.2 KB, 68 views)
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