[Argus25]

... I've attached a picture of what a properly separated V sync should approximately look like (with or without equalizing pulses) at the grid of a vertical osc stage with the osc disabled. In circuits where it gets injected into the plate load area it simply gets transformed by the blocking osc transformer to become a + going pulse at the grid.

When the level is too low and especially if it is over integrated, at the moment the grid voltage is rising, about to bring the vert osc valve into conduction, it is getting to the point where a very tiny grid voltage transient (such as interference from H pulse on the supply rail, or from nearby wiring) trigger the vert osc into the next cycle instead, then the half line delay is lost and line pairing occurs.

With a better decent amplitude and properly separated V sync, the V osc is triggered definitely by that timing, at a time where its grid voltage is lower (more negative) and therefore the osc stage less sensitive to interfering H pulses that could trigger it instead.

So the bottom line is if the V sync pulses are too weak and over integrated with a slow rising edge, more likely line pairing will occur.

Also with regard to the TV22 circuit, normally the diode is not required and if you look at their circuit, there is no DC return path on the diode's anode, the only possible path is the diode leakage itself which is ill controlled or leakage in faulty aging capacitors.

Also, with this circuit it is very important that the filter capacitor C7 0.1uF is in perfect order, or H pulses will modulate the primary of the blocking osc transformer and make the line pairing worse.