Re: MK14 schematic revisions
An additional difficulty is that SOC changed which gates within packages were used, so the pin numbers in the v2 schematic are not the same as in the note... perhaps they were referring to a v1 board!
However I've worked it out (please excuse the rubbish image editing!)
Basically the reset circuit is reworked to free up a NOT gate and the spare gates used to NAND the inverted A9,10,11 signals with RDS or WDS.
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