[Mark1960]

I’ve been looking at the output of the clocked serial and the clock output. At the start of each line, when the synchronous tx is initialised, the clock output is driven low and the tx output is driven high. There is then a short delay where tx is high and clock stays low, which causes the white band down the left edge of the screen. The clock then starts clocking out the data on the rising edge of each clock cycle.

It might be possible to register the tx output to eliminate the white band. We would want to register the tx output on the falling edge of each clock cycle.

Looking at the spec for the PIC it doesn’t seem to be possible to change the clock polarity or phase in the synchronous Tx mode that is used by ortonview.

Unfortunately the common 74x74 D type flip flop registers data on the rising edge of each clock. We can invert the clock, and this can be done with one half of the 74x74, but this then delays the rising edge at the input of the D type and would capture the unwanted high tx level at the start of the line and we would still see the white band.

We can avoid registering the unwanted tx high level by adding an RC delay. This would need to be longer than the propagation delay of the inverter but less than the width of the clock pulses. I think this is just about possible.

This is going to shift the display image half a pixel to the right, but it should be a fixed offset and would probably not be noticed.

One thing I’m not sure about is what happens when the tx clock output pin is used to read the state of P4. If it clocks the flip flop it could leave a horizontal bar on the display until the next tx clock. I tried linking P4 to ground but didn’t see any difference on the tx clock output.

I may just give it a try and see if it works.