[pitbuell94]

Hi Dears Sirs,

This is my last design concerning my FIFO with asynchrone write and read operation.

Hope this 'll run in normal way.

For those we need english translation concerning this code, I can do it.

I'm surrely not the best in VHDL, but I can give some help.

Have a nice week-end.

Frédéric Cabanes.