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The major unknown would be the noise level. Since the oscillator is running at low level, would'nt this imply a highish close-in noise spectrum ?
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This was probably the main question in the thread so maybe it's best to focus on this rather than get into specific oscillator types.
By close in phase noise I'm assuming you mean phase noise offsets in the range 100Hz to 50kHz. A voltage level of 224mV rms into 50R is about 1mW or 0dBm. This is quite a healthy signal level for a local oscillator. A typical level for a diode ring mixer might be +7dBm so this isn't much higher in level. So I don't think there will be any issues at all with close in phase noise.
You can get some idea of the power in the resonator of an oscillator by looking at the Vpkpk in the resonator and doing a few sums based on the loaded Q of the tank, the frequency and the capacitance (or inductance) in the tank. For example, At 11MHz with a loaded Q of 50 and a resonator capacitance of 100pF and about 10Vpkpk in the resonator the power would be a couple of mW or so.
If the noise figure of the active device (including resonator loss and non linearity effects) totalled 8dB and you chose a BJT oscillator there is enough info there to predict the close in phase noise fairly well. I find that the corner frequency for the flicker noise for a BJT is usually around 5kHz at these frequencies. Armed with the above info, there is enough there to do a crude prediction of phase noise using Leeson's equation.
The result is as the plot below. This is for a BJT. If a JFET is used I think the flicker corner frequency will be different. It could be 10-15kHz. Some FET types have really high flicker corner frequency. However, if 15kHz is entered then the phase noise doesn't degrade that much with the JFET. It only degrades the close in phase noise a couple of dB or so. So I haven't bothered to post up the JFET version of the plot below as it will be very close to this.
So as long as you end up with a decent loaded Q of >40 and something in the ballpark of 10Vpkpk in the resonator of your JFET based 11MHz Franklin oscillator (assuming a resonator capacitance in the ballpark of 70-100pF) you can't really go wrong with the close in phase noise of a free running VFO like this as long as there isn't a gross error in the overall design somewhere.
Where you might hit problems with the VE3RF circuit is in the spread in Idss for your chosen JFET. I think this will affect the starting gain quite a bit because it only takes a small change in Idss (away from maybe 4mA) to radically change the DC voltage at the drain of each JFET at startup. If this voltage gets quite low (idss approaching 6mA?) then I think the startup gain will begin to collapse. So this circuit is probably OK if you don't mind selecting a JFET with a sensible Idss figure that suits this circuit.
The other issue is how you extract energy from the oscillator without spoiling the loaded Q and without degrading the ultimate noise floor of your system. Get it wrong and you could end up with a far out noise floor plateau of -145dBc/Hz out to several hundred kHz. This will happen if you degrade the signal level too much with respect to thermal noise at -174dBm/Hz. Even if you then try and amplify it back up again, the damage is done and the noise plateau will remain!
However, the close in phase noise wouldn't be affected unless the buffer was somehow able to load the oscillator resonator or affect the overall loop response quite badly.