Ortonview PCB
 

Well since I've been working on this schematic to make an Ortonview PCB so that I can tinker with the firmware which still has a few minor niggles to work out, I thought I'd put the schematic up here in hopes someone will give it a look over and spot any mistakes/bad decisions/missing things that are likely to be in there. The board is intended to plug into the back of a "Issue VI" board using the signals put on the edge connector by the latest release. I have included the essential 1.5k memory hole filler (with optional battery back up) and an option random noise generator clocked from NADS that can be connected to a sense pin or SIN to make random numbers for all those games people are bound to start writing!

I'm going to try to start work on the actual PCB design next week.

Re: Ortonview PCB
 

Just had a quick look, in the short term it is also going to need pads for 4 x SM or through hole (or both) small value capacitors from A8-A11 to 0V as they are they are the essential 'dirty fix' to solve the problem where the system kept writing to address 'n' in one or more pages.

More ideally, add 2 x 74LS365 (6 x bidirectional buffers) in the VDU address bus (same as per the original VDU) so that the VDU address lines are cleanly disconnected from the MK14 address bus when the VDU is not trying to access it. You will remember that on Ortonview, the address line outputs from the VDU are just put into input mode but that does not properly disconnect them from the MK14 address bus and causes some loading on A8-A11.

It would obviously be much more of a chore to wire these buffers up on a veroboard build but if there is to be a PCB, then the two extra sockets and ICs would add no more than five extra minutes on the build. I would say this would be more directly necessary than a noise / random generator although I do like that idea.

Needless to say, you can count me in for one of these if they ever get to the point of being made. If you get to that point let us know how much you are going to want for them and - sorry to have to say this, but I suggest you don't put the design files in the public domain.

Re: Ortonview PCB
 

The buffers are a good idea, I presume they will be enabled by the NENIN signal. The can always be replaced by wire links if not required. The PCB is intended to be an "experimental" board anyhow, so unpopulated parts are already a likelihood likewise I will put pads in for the capacitors - I remembered you and Tim trying them but couldn't recall if they ended up being neededd.
The Random Noise generator is really for my "Twonky" experiments for which the extra memory will also be useful....
I think I will probably keep the design files to myself for a bit at least.

Re: Ortonview PCB
 

Looking good - I like the way you have fully flexible jumpers for hand control of the options and also to hook up the RAM/IO controls if wanted.

One other idea might be to build in space for the recommended audio out / single step circuits from the manual (1 chip each) so there is an all in one expansion card to what was available at the time? These could be a small patch area that did not tie to specific chips - if space allowed... ?

I of course would also be very interested in one of these and probably sensible to control the making...

I will take a closer look at the circuit as well over the next day or so when time allows to see if I can spot any errors.

Re: Ortonview PCB
 

As the firmware currently stands, yes, they really are needed and I am not personally convinced that that problem has a firmware solution since there is no way for the firmware to influence that problem - as the PIC ports used don't have a genuine hands-off (tristate) mode, and can only be input or output. That's why I suggest adopting the same solution as the original VDU - 'proper' tristate buffers in between the VDU 'address bus' and the actual address bus.

It might still be possible to play with the timing of the point at which the port pins switch from input to output, and, as has been pointed out before, the port pin directions can only be changed one port at a time, so maybe changing the order in which the A0-A7 port and A8-A11 port have their directions changed over could also make a difference.

Re: Ortonview PCB
 

Well I've reworked it so the buffers and experimental capacitors can be added. It will make the layout more of a challenge, but thats part of the fun :-D:o:-D

Re: Ortonview PCB
 

I think you have the address lines to the RAM from the wrong side of the buffers. This would prevent access to the RAM from the SCMP.

Is the diode supply switching to the RAM something you have already tested? I have experimented with putting the switching in the ground connection using a bc108 to avoid voltage drop as this also disables write enable when main supply is off. I wasn’t convinced this was really working well. I think I prefer to use a MAX818 or similar to also disable chip enable, though it might not be simple to connect the reset output to the SCMP via the edge connector.

If you have space use a small slide switch for the write protect instead of just a two pin header.

I don’t think you want pin 18 and 21 on the ram connected.

Re: Ortonview PCB
 

If you can rework things that fast we'll expect the finished PCB design shall we say...

...Thursday?

I was slightly thrown by the way the A... and UA... lines appear to converge in the same single wire/bus but I guess that's just Kicad's way of doing things, as the sources and destinations of the two groups of signals are indicated at the device pins themselves.

Mark: Notice that there are two address buses, the 'UA... bus and the 'A'... bus. I don't think they are actually connected together although they look as though they are. The only lines passing through the buffers are the UA... lines from the PIC, the 'A' lines I'm guessing go straight between the RAM and the System A... lines. (See above paragraph).

Re: Ortonview PCB
 

The 'Top Page' output needs to be available on more than one pin header because it may occasionally need to be linked to more than just one of the page select inputs - for example it may also be linked to graph / chars to change from one mode to the other half way through the screen and maybe even also to 'swap pages' depending on whether you want the graphics half to be on the upper half rather than the lower half. So right there is an example where you might need to have three jumpers or links going to Top Page.

I would also provide for a modest value series resistor in the 'Top Page' signal output from the chip because with the amount of patchability available it would be quite possible for Top Page (an output) to end up connected to a page select input which is shorted to GND via a closed switch, or to end up in opposition to an 8154 port pin which is set to be an output. That's an especially expensive mistake to make on a real SOC VDU but you don't want to make it too easy for Tim to fry all of his 877s, either.

Re: Ortonview PCB
 

The annotations on the buses are correct, so the memory will connect to the unbuffered address bus, but your right in that the diagram is misleading. I will have to redraw the blue line connecting the memory to rest of the circuit to make this clearer. perhaps changing the labels from UAx to BAx would be more appropriate too.

I have tried using diodes to route power to chips but not this one specificaly. However the M5M5117 operates down to 4.5v so the ~0.2v schottky diode drop should not cause problems. If it does, I'll just remove the battery function and jumper the diodes.

Nice spot on pin 18/21, not sure how that happened.

Thanks for spotting these things, its exactly why I post this!
Ian

Re: Ortonview PCB
 

OK I see that now, I never did like showing a bus connection in a schematic with more than one type of signal in the bus. I saw you had a separate bus for data and just assumed you were following the same standard.

One thing to watch out for is that the chip enable will be held low when 5v supply is off. Some ram chips will lock out the chip enable when their supply is below a threshold. I’m not sure if the M5M5117 does that. If it doesn’t then the chip is enabled on battery supply and can run the battery down a bit quicker than it should.

Re: Ortonview PCB
 

Good point. Maybe I need to look at the enable logic, or put a pullup on /S so that when power is taken off U1 the chip is not enabled, although I'd have to check that won't cause problems if U1 is not powered. As I said, the battery backup was a kind of "nice to have".

Re: Ortonview PCB
 

I think parasitic diodes in the output of U1 would still pull the chip select down when 5v is turned off.

R1, R2 and R3 are also probably going to be draining the battery when 5v is off.

I think R1 and R3 could pull up to 5v instead of the battery supply.

You could power U1 from the battery supply and remove R2, but then you probably don’t want to use the spare gate as an inverter for the address buffer enable.

The 74hc02 might not work with address input levels from the SCMP, and might be better to use 74hct02. I wasn’t sure if you deliberately picked the hc or if that was just a package that was available. Then the 74hct02 probably shouldn’t be powered from the battery as it might not behave itself at battery supply voltages.

If you have 74hct4070 instead of the 4070, or 74hct86, you could use the spare gate as an inverter. I don’t think a cd4070 would be fast enough for the address buffer circuit. But this would mean the prbs generator is not completely separate from the rest of the board.

Re: Ortonview PCB
 

I'm going to have to get a 74HCT02 and test it before pushing the button on the PCBs! In any case, this iteration of the PCB is meant to contain "experimental" features so I can see how it works in practice. But it won't be too hard to get a 74HCT02, not power it and measure the voltage on the output when it is pulled up via a resistor. This will also tell me how much current is being pulled through the resistor and if that is excessive and likely to cause problems for the IC or battery. I already have a couple of memory chips so I can wire those up to see the effect of R1,2,3 on battery consumption too.
They are deliberately large values, so this is mitigated somewhat. They are intended to pull up to whatever the Vcc pin of the memory chip is, whether it is from the PSU or battery.
The HC part was what came up tbh. I would probably use the HCT part in practice. I will amend the diagram appropriately.
The address buffer uses the spare gate from the 74HC(T)02, which previously was inverting the TOP signal as I could no longer remember why I wanted to do this.

Re: Ortonview PCB
 

Series resistors shouldn't be a problem, about 1k? Wouldn't like to deplete Tims supply any further :D

Re: Ortonview PCB
 

In my defense I have only fried 2 8154, 1 74L86 and two 877's before I learned my lesson :)

Re: Ortonview PCB
 

RIP 8154's. Looks like the replacement project just got a bit more urgent :laugh1:

Re: Ortonview PCB
 

Seriously though, this is why adding these little safety catches - a 2p resistor (which might potentially save an old bit of silicon costing 100 times as much) is worthwhile. There is an ever decreasing supply of these expensive old devices out in the wild.

Maybe the pulldown switches on the page select and mode select inputs should also have low value series resistors in case 8154 outputs are ever accidentally connected to them when the switches are in the short-to-ground position.

Re: Ortonview PCB
 

How low a resistance will protect the 8154? The data sheet I have for the 8154 doesn't specify a maximum output current, and I'd worry if the resistance was too high then the 8154 wouldn't be able to pull down the option pins enough to register as a '0' on the PIC.. Even a 500 ohm resistor would only limit current to 10mA but would require the 8154 to pull the pin down to less than ~0.5v.

Re: Ortonview PCB
 

Well, I was suggesting putting the resistors in series with the pulldown switches rather than in series with the 8154 port pins, so their only function is to stop 8154 pins which are in output mode (Or indeed Flag outputs, which Tim likes to use) being shorted directly to GND in the event that any pulldown switch gets moved to the closed position.

Obviously the ratio of the switch series resistors and the pullup resistors will have to be such that closing a switch still imposes a valid logic 0 level when there is nothing else (8154 output, Flag output) driving the line to 5V or 0V.

Don't worry too much about the actual values, just provide somewhere to insert them or insert links and we will experiment for best value.