-------------------------------------------------------------------------------- -- Company: -- Engineer: -- -- Create Date: 12:24:38 02/07/2011 -- Design Name: -- Module Name: D:/Documents and Settings/FIFOdu07022011/test_bench_fifo.vhd -- Project Name: FIFOdu07022011 -- Target Device: -- Tool versions: -- Description: -- -- VHDL Test Bench Created by ISE for module: fifo -- -- Dependencies: -- -- Revision: -- Revision 0.01 - File Created -- Additional Comments: -- -- Notes: -- This testbench has been automatically generated using types std_logic and -- std_logic_vector for the ports of the unit under test. Xilinx recommends -- that these types always be used for the top-level I/O of a design in order -- to guarantee that the testbench will bind correctly to the post-implementation -- simulation model. -------------------------------------------------------------------------------- LIBRARY ieee; USE ieee.std_logic_1164.ALL; USE ieee.std_logic_unsigned.all; USE ieee.numeric_std.ALL; ENTITY test_bench_fifo IS END test_bench_fifo; ARCHITECTURE behavior OF test_bench_fifo IS -- Component Declaration for the Unit Under Test (UUT) COMPONENT fifo PORT( rst : IN std_logic; wr_en : IN std_logic; wr_clk : IN std_logic; wr_data : IN std_logic_vector(7 downto 0); rd_en : IN std_logic; rd_clk : IN std_logic; rd_data : OUT std_logic_vector(7 downto 0) ); END COMPONENT; --Inputs signal rst : std_logic := '1'; signal wr_en : std_logic := '0'; signal wr_clk : std_logic := '0'; signal wr_data : std_logic_vector(7 downto 0) := (others => '0'); signal rd_en : std_logic := '0'; signal rd_clk : std_logic := '0'; --Outputs signal rd_data : std_logic_vector(7 downto 0); -- Clock period definitions constant wr_clk_period : time := 20ns; constant rd_clk_period : time := 20ns; BEGIN -- Instantiate the Unit Under Test (UUT) uut: fifo PORT MAP ( rst => rst, wr_en => wr_en, wr_clk => wr_clk, wr_data => wr_data, rd_en => rd_en, rd_clk => rd_clk, rd_data => rd_data ); -- Clock process definitions wr_clk_process :process begin wr_clk <= '0'; wait for wr_clk_period/2; wr_clk <= '1'; wait for wr_clk_period/2; end process; rd_clk_process :process begin rd_clk <= '0'; wait for rd_clk_period/2; rd_clk <= '1'; wait for rd_clk_period/2; end process; -- Stimulus process stim_proc: process begin wait for 10ns; wait for wr_clk_period*10; rst <= '0'; wait; end process; END;