Hi Sean,
Quote:
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Originally Posted by m1ecy
I wonder if the slight vertical "jitter" on the picture is just a bug to iron out?
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Very probably - XORing the syncs seems enough to prove the concept actually works; but in the long term it's not ideal. There's half the correct number of pulses and those that are there have the negative-going transition delayed by the width of the line-sync pulse compared to where they should be.
Now I've got that Pye monitor (thanks again for bringing it, that was really appreciated) I have a much better display device (after I've refurbished it a bit) which will help with hardware improvements - the first is to devise means to generate syncs which bear some relationship to the standard. I think a PLL may be involved.
Still, I don't think it's too bad for an experimental system; it even worked from booting up right through the day with no problems
Regards, Kat